The present invention relates to a dual in-line memory module (DIMM), and more particularly, to a DIMM that can perform a test mode operation using extra input/output (IO) pads.
In fabricating a semiconductor memory device, it is advantageous that the kind of the semiconductor memory device as a final product is determined at a later stage of the fabrication process.
The reason for this is that as the specific kinds of the product are determined later, more operations can be shared in fabricating various kinds of products.
Specifically, such a sharing conception plays an important role in fabricating the semiconductor memory device. In producing the semiconductor memory device based on a few items/mass productions, the efficiency of the fabricating process can be a crucial factor for competitiveness of manufactures.
One of the important specifications of the semiconductor memory device is a bit organization. The bit organization is expressed by x1, x4, x8, etc. This represents the number of memory cells selected by one address.
That is, the bit organization represents the number of memory cells that are simultaneously read or written by one addressing, and the semiconductor memory devices can be differently configured even though they have the same capacity.
For example, in case of an x4 organization, when one address is inputted, four memory cells are accessed and four bit data are outputted. In case of an x16 organization, when one address is inputted, sixteen memory cells are accessed and sixteen bit data are outputted.
Accordingly, a 16M DRAM can have different bit organizations, for example, 16M×1, 4M×4, 2M×8, etc. The 16M×1 bit organization means that the semiconductor memory device has 16M number of 1-bit cells, and the 4M×4 organization means that the semiconductor memory device has 4M number of 4-bit cells. Also, the 2M×8 organization means that the semiconductor memory device has 2M number of 8-bit cells.
In a viewpoint that the bit organization represents the number of memory cells-that are simultaneously read or written by one addressing, the semiconductor memory device can be expressed by an operation mode. Therefore, it should be noted that the bit organization expression and the operation mode expression can exist together.
That is, the x1, x4 and x8 operation modes of the semiconductor memory device may be used to determine how many data pins the semiconductor memory device sealed by packaging will have.
For example, the x1 operation mode uses one data I/O pin or two data pins separated into a data-in pin and a data-out pin.
Likewise, the x4 operation mode uses four data I/O pins or eight data pins separated into data-in pins and data-out pins.
In addition, the x8 operation mode uses eight data I/O pins or sixteen data pins separated into data-in pins and data-out pins.
The operation modes of the semiconductor memory device vary depending on its usage field.
For example, the x16, further x32, organization is used for a semiconductor memory device having high data bandwidth for the fields requiring high performance, for example a graphic field. The x8 and x4 organizations are widely used in PC systems and server systems.
If fabricating semiconductor memory devices having different operation modes depending on the usage fields and different number of data pins, designs during their fabrication must be changed. Therefore, it is contrary to the sharing conception that it is advantageous to determine the specific kind of the product at a later stage of the fabricating process.
Hence, the DRAM does not have the above-described bit organization at a wafer level during its fabricating process, and the DRAM is assembled in the x4 or x8 bit organization during packaging.
Additionally, most of semiconductor memory devices are produced in a system form for the purpose of high capacity and high performance.
In some applications, e.g., a PC system, the semiconductor memory devices are produced in a module architecture, in which they are integrated on a single printed circuit board (PCB), and the memory modules are mounted in slots of the systems.
Among various types of the memory modules, a dual in-line memory module (DIMM) is widely used.
The DIMM can have various shapes and sizes, and a 168-pin, 184-pin or 240-pin DIMM are available.
The most widely used DIMM has the 184-pin configuration. Because the 184-pin DIMM has perfect x64 data buses, data can be transmitted with a 64-bit data bandwidth. Therefore, the 184-pin DIMM is used as main memory in Pentium or higher desktop systems or server systems.
As described above, one DIMM can have the x64 organization at the module level. In this case, sixteen x4 DRAMs or eight x8 DRAMs are mounted on one module. Meanwhile, one module can have an x72 organization at the module level. In this case, the additional eight bits of the x72 DIMM may be used to control data buses and check partial bit error.
FIG. 1 is a block diagram illustrating a conventional memory controller and a conventional DIMM.
Referring to FIG. 1, a plurality of DIMMs 100 and 170 are connected to one memory controller.
Each of the first DIMM 100 and the second DIMM 170 includes nine DRAMs, each of which has eight data pins DQ0 to DQ7 and clock pins CLK1 and CLK2.
In addition, eight bits DQ64 to DQ71 are added to the DIMMs 100 and 170 and used to control data buses and check a partial bit error.
However, it is impossible for the conventional DIMMs 100 and 170 to enter a test mode or a built-in-self-test (BIST) mode and modify the internal structure of the DRAMs.
That is, the internal logic of the DRAM can be modified using a combination of a command and an address, or a defect test can be performed through a timing control. However, the DIMMs 100 and 170 cannot enter a test mode because a command and an address cannot be applied to the respective DRAMs.
In case that the test cannot be performed in the state of the DIMM 100 and 170, if an error that has not happened during the test of the DRAMs occurs in the DIMMs 100 and 170, the cause of the error cannot be found out.